The present invention relates generally to data pattern generators and more particularly to a data pattern generator that can shift edge positions of the output data pattern as desired.
In developing an electronic circuit, a trial circuit is made wherein a preceding block of the circuit may not be finished. A signal generator may simulate the preceding block to provide signals that the preceding block would output if it was completed.
Digital circuit processes are not always ideal resulting in the shifting of the rising and falling edges in a data pattern of a pulse train from the ideal positions, which appears as jitter of the rising and falling edges. A jitter tolerance is usually specified for digital circuits so that the circuit works well even if there rising and falling edges of the input pulse train has jitter.
To confirm the circuit under development meets specified jitter tolerances, a data pattern having jitter is provided to the digital circuit to confirm the operation of the circuit. According to this need, there is a data pattern generator that can provide data patterns in which the rising and falling edges are shifted relative to the ideal positions as specified by a user.
U.S. Pat. No. 5,389,828 by Tago discloses a pulse width adjusting circuit that shifts rising or falling edge positions of pulses in an input pulse train. Referring to FIG. 1, a comparator 4 compares an input pulse to an output of a digital to analog converter (DAC) 2 to shift the rising and falling edge positions of the input pulse. The variable time delay of the rising and falling edges of the output pulse of the comparator 4 is a function of the input control signal to the DAC 2. A delay circuit 6 also receives the input pulse and applies a time delay to the input pulse. A logic circuit 8 receives the time delayed input pulse from the delay circuit 6 and the output pulse of the comparator 4 and shifts the rising edge position of the output pulse from the comparator 4 as a function of the control signal to the DAC 2 and the falling edge position as a function of the delay circuit 6.
As described, the pulse width adjustable circuit disclosed in U.S. Pat. No. 5,389,828 independently controls trailing edge of the delayed pulse with respect to the leading edge using the delay circuit 6. There are various types of delay circuits but, at the present, the load time for delay circuits is to slow to allow the setting of the leading or trailing edges of a gigahertz pulse trail in real time.
US publication No. 2004/0135606 discloses an invention to overcome the shortcoming of the long setting time of the delay circuit. The invention has two delay blocks with one block delays an input pulse train while the other block changes the setting of the delay time. But this circuit requires the detection of an edge position of the input pulse train so as not to break a pulse when the circuit switches blocks because the input pulse train is asynchronous with the system clock of the circuit. This operation makes it impossible to change the edge positions of the respective pulses in real time.